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Compiler-Aware Heterogeneous Graph Learning for HLS QoR Prediction and Design Space Exploration

High-level synthesis (HLS) design space exploration seeks Pareto-optimal designs within vast directive configuration spaces. Existing graph neural network approaches rely mostly on single-graph, homogeneous-style representations that do not model …

Reliable Control-Layer Routing for Microfluidic Biochips via Bayesian Optimization

A Two-Layer Decoupled Synthesis Framework for Uncertain Biochemical Protocols on Active-Matrix Digital Microfluidic Platforms

FlatDD: A High-Performance Quantum Circuit Simulator using Decision Diagram and Flat Array

Towards Secure and Efficient DNN Accelerators via Hardware-Software Co-Design

AgeBalance: Low-Cost Lifetime Extension for SRAM-based PIM Accelerators

Efficient Multi-Array Parallel Scheduling for In-Memory Computing

CHOP: Clustered Hybrid Optimization for Logic Synthesis with Self-Supervised Prediction

JPnR: A Length-Matching Placement and Routing Framework for Single-Flux-Quantum Circuits

Efficient Cartesian Genetic Programming-based Automatic Synthesis Framework for Reversible Quantum-Flux-Parametron Logic Circuits