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AnalogVerifier: A Neuro-Symbolic Framework for Analog Circuit Verification

Expert-level Leaf Cell Layout Generation via Preference-Optimized LLM

THLR: A Top-down Hierarchical Logic Rewrite Framework for Xor-Majority-Inverter Graphs

SAT-Helper: A Multi-Agent System for Adaptive Optimizing Large-Scale Conjunctive Normal Form

Chariot: Compiler-Aware Heterogeneous Graph Representation Learning for Automated HLS Optimization

ELMBA: Escape from Local Minima in Buffer and Splitter Insertion for AQFP Circuits

JSPlace: A Shape-Controllable and Length-Matching Placement for Rapid Single-Flux-Quantum Circuits

MappingEvolve: LLM-Driven Code Evolution for Technology Mapping

ModuPlace: LLM-Assisted Modular PCB Placement via Preference-Optimized Constraint Graph Generation

RECALLS: Reinforcement Learning Enhanced Generative Model for Logic Synthesis Optimization