Good Good Study and Day Day Up
Home
News
Publications
1
AICL: Alignment-Driven Iterative Closed-Loop Optimization for Layout Pattern Clustering
APCG: Automatic Placement Constraint Generation for Analog Circuits
LibPilot: Knowledge-Constrained Dual-Agent Reasoning for Standard Cell Library Tuning
AnalogVerifier: A Neuro-Symbolic Framework for Analog Circuit Verification
Expert-level Leaf Cell Layout Generation via Preference-Optimized LLM
THLR: A Top-down Hierarchical Logic Rewrite Framework for Xor-Majority-Inverter Graphs
Late Breaking Results: A Multi-Agent System for Adaptive Optimization of Large-Scale Conjunctive Normal Form
Chariot: Compiler-Aware Heterogeneous Graph Representation Learning for Automated HLS Optimization
JSPlace: A Shape-Controllable and Length-Matching Placement for Rapid Single-Flux-Quantum Circuits
MappingEvolve: LLM-Driven Code Evolution for Technology Mapping
»
Cite
×