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SAT-Helper: A Multi-Agent System for Adaptive Optimizing Large-Scale Conjunctive Normal Form

Chariot: Compiler-Aware Heterogeneous Graph Representation Learning for Automated HLS Optimization

ELMBA: Escape from Local Minima in Buffer and Splitter Insertion for AQFP Circuits

JSPlace: A Shape-Controllable and Length-Matching Placement for Rapid Single-Flux-Quantum Circuits

MappingEvolve: LLM-Driven Code Evolution for Technology Mapping

ModuPlace: LLM-Assisted Modular PCB Placement via Preference-Optimized Constraint Graph Generation

RECALLS: Reinforcement Learning Enhanced Generative Model for Logic Synthesis Optimization

eLogic: A E-Graph-based Logic Rewriting Framework for Majority-Inverter Graphs

Majority-Inverter Graph (MIG) emerges as a promising data structure for logic optimization and synthesis, offering a more compact representation for logic functions compared to traditional AND/OR-Inverter graphs. Consequently, the MIG finds …

PCB-Migrator: Automated PCB PnR Migration

Despite the availability of numerous frameworks and tools for automated PCB placement and routing, the industry still relies heavily on expert designers to ensure layout reliability and performance. However, when design requirements change, such as …

DCLOG: Don't Cares-based Logic Optimization using Pre-training Graph Neural Networks

Logic rewriting serves as a robust optimization technique that enhances Boolean networks by substituting small segments with more effective implementations. The incorporation of don't cares in this process often yields superior optimization results. …