Publications

(2025). JBSA: A Bit-Serial Accelerator for Deep Neural Networks Using Superconducting SFQ Logic. ACM International Conference on Supercomputing (ICS).

(2025). Late Breaking Results: Hybrid Logic Optimization with Predictive Self-Supervision. Proceedings of the 62nd Design Automation Conference (DAC). (22.6% acceptance ratio)

(2025). SeDA: Secure and Efficient DNN Accelerators with Hardware/Software Synergy. Proceedings of the 62nd Design Automation Conference (DAC).

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(2025). Efficient Cartesian Genetic Programming-based Automatic Synthesis Framework for Reversible Quantum-Flux-Parametron Logic Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).

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(2025). TeMACLE: A Technology Mapping-Aware Area-Efficient Standard Cell Library Extension Framework. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).

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(2024). HeLO: A Heterogeneous Logic Optimization Framework by Hierarchical Clustering and Graph Learning. Proceedings of the 2025 International Symposium on Physical Design (ISPD).

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(2024). Buffer and Splitter Insertion for Adiabatic Quantum-Flux-Parametron Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).

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(2024). RABER: Reliability-Aware Bayesian-Optimization-based Control Layer Escape Routing for Flow-based Microfluidics. Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

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(2024). FlatDD: A High-Performance Quantum Circuit Simulator using Decision Diagram and Flat Array. Proceedings of the 53rd International Conference on Parallel Processing (ICPP).

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(2024). RCGP: An Automatic Synthesis Framework for Reversible Quantum-Flux-Parametron Logic Circuits based on Efficient Cartesian Genetic Programming. Proceedings of the 61st Design Automation Conference (DAC).

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(2024). JPlace: A Clock-Aware Length-Matching Placement for Rapid Single-Flux-Quantum Circuits. Proceedings of the 27th Design, Automation & Test in Europe Conference & Exhibition (DATE). (co-first author)

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(2023). Exact Logic Synthesis for Reversible Quantum-Flux-Parametron Logic. Proceedings of the 42nd IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

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(2023). DLPlace: A Delay-Line Clocking-Based Placement Framework for AQFP Circuits. Proceedings of the 42nd IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

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(2023). JRouter: A Multi-Terminal Hierarchical Length-Matching Router under Planar Manhattan Routing Model for RSFQ Circuits. Proceedings of the 2023 on Great Lakes Symposium on VLSI (GLSVLSI).

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(2023). BOMIG: A Majority Logic Synthesis Framework for AQFP Logic. Proceedings of the 26th Design, Automation & Test in Europe Conference & Exhibition (DATE).

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(2023). A Global Optimization Algorithm for Buffer and Splitter Insertion in Adiabatic Quantum-Flux-Parametron Circuits. Proceedings of the 28th Asia and South Pacific Design Automation Conference (ASPDAC).

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(2022). JBNN: A Hardware Design for Binarized Neural Networks using Single-Flux-Quantum Circuits. IEEE Transactions on Computers (TC).

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(2022). A survey on superconducting computing technology: circuits, architectures and design tools. CCF Transactions on High Performance Computing (CCF-THPC).

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(2021). Equivalence Checking for Superconducting RSFQ Logic Circuits. Proceedings of the 2021 on Great Lakes Symposium on VLSI (GLSVLSI). (Best Paper Nomination)

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(2020). Design Automation Methodology from RTL to Gate-Level Netlist and Schematic for RSFQ Logic Circuits. Proceedings of the 2020 on Great Lakes Symposium on VLSI (GLSVLSI).

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