Publications

(2026). SAT-Helper: A Multi-Agent System for Adaptive Optimizing Large-Scale Conjunctive Normal Form. Proceedings of the 63nd Design Automation Conference (DAC). (Corresponding Author)

(2026). Chariot: Compiler-Aware Heterogeneous Graph Representation Learning for Automated HLS Optimization. Proceedings of the 34th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM).

(2026). ModuPlace: LLM-Assisted Modular PCB Placement via Preference-Optimized Constraint Graph Generation. Proceedings of the 63nd Design Automation Conference (DAC). (Corresponding Author)

(2026). MappingEvolve: LLM-Driven Code Evolution for Technology Mapping. Proceedings of the 63nd Design Automation Conference (DAC).

(2026). JSPlace: A Shape-Controllable and Length-Matching Placement for Rapid Single-Flux-Quantum Circuits. Proceedings of the 63nd Design Automation Conference (DAC).

(2026). ELMBA: Escape from Local Minima in Buffer and Splitter Insertion for AQFP Circuits. Proceedings of the 63nd Design Automation Conference (DAC).

(2026). Efficient Multi-Array Parallel Scheduling for In-Memory Computing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).

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(2026). RECALLS: Reinforcement Learning Enhanced Generative Model for Logic Synthesis Optimization. IEEE International Symposium on Circuits and Systems (ISCAS).

(2025). CHOP: Clustered Hybrid Optimization for Logic Synthesis with Self-Supervised Prediction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).

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(2025). PCB-Migrator: Automated PCB PnR Migration. Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE).

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(2025). eLogic: A E-Graph-based Logic Rewriting Framework for Majority-Inverter Graphs. Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE).

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(2025). JPnR: A Length-Matching Placement and Routing Framework for Single-Flux-Quantum Circuits. IEEE Transactions on Computers (TC).

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(2025). Partitioning-free 3D-IC Floorplanning. Proceedings of the 31st Asia and South Pacific Design Automation Conference (ASPDAC).

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(2025). DCLOG: Don't Cares-based Logic Optimization using Pre-training Graph Neural Networks. Proceedings of the 31st Asia and South Pacific Design Automation Conference (ASPDAC).

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(2025). J2Place: A Multiphase Clocking-Oriented Length-Matching Placement for Rapid Single-Flux-Quantum Circuits. Proceedings of the 44th IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

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(2025). ChronoTE: Crosstalk-Aware Timing Estimation for Routing Optimization via Edge-Enhanced GNNs. Proceedings of the 44th IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

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(2025). An Optimal DFF-Oriented Technology Legalization Algorithm for Rapid Single-Flux-Quantum Circuits. Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI).

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(2025). JBSA: A Bit-Serial Accelerator for Deep Neural Networks Using Superconducting SFQ Logic. ACM International Conference on Supercomputing (ICS).

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(2025). Late Breaking Results: Hybrid Logic Optimization with Predictive Self-Supervision. Proceedings of the 62nd Design Automation Conference (DAC). (22.6% acceptance ratio)

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(2025). SeDA: Secure and Efficient DNN Accelerators with Hardware/Software Synergy. Proceedings of the 62nd Design Automation Conference (DAC).

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(2025). Efficient Cartesian Genetic Programming-based Automatic Synthesis Framework for Reversible Quantum-Flux-Parametron Logic Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).

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(2025). TeMACLE: A Technology Mapping-Aware Area-Efficient Standard Cell Library Extension Framework. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).

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(2024). HeLO: A Heterogeneous Logic Optimization Framework by Hierarchical Clustering and Graph Learning. Proceedings of the 2025 International Symposium on Physical Design (ISPD).

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(2024). Buffer and Splitter Insertion for Adiabatic Quantum-Flux-Parametron Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).

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(2024). RABER: Reliability-Aware Bayesian-Optimization-based Control Layer Escape Routing for Flow-based Microfluidics. Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

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(2024). FlatDD: A High-Performance Quantum Circuit Simulator using Decision Diagram and Flat Array. Proceedings of the 53rd International Conference on Parallel Processing (ICPP).

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(2024). RCGP: An Automatic Synthesis Framework for Reversible Quantum-Flux-Parametron Logic Circuits based on Efficient Cartesian Genetic Programming. Proceedings of the 61st Design Automation Conference (DAC).

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(2024). JPlace: A Clock-Aware Length-Matching Placement for Rapid Single-Flux-Quantum Circuits. Proceedings of the 27th Design, Automation & Test in Europe Conference & Exhibition (DATE). (co-first author)

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(2023). Exact Logic Synthesis for Reversible Quantum-Flux-Parametron Logic. Proceedings of the 42nd IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

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(2023). DLPlace: A Delay-Line Clocking-Based Placement Framework for AQFP Circuits. Proceedings of the 42nd IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

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(2023). JRouter: A Multi-Terminal Hierarchical Length-Matching Router under Planar Manhattan Routing Model for RSFQ Circuits. Proceedings of the 2023 on Great Lakes Symposium on VLSI (GLSVLSI).

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(2023). BOMIG: A Majority Logic Synthesis Framework for AQFP Logic. Proceedings of the 26th Design, Automation & Test in Europe Conference & Exhibition (DATE).

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(2023). A Global Optimization Algorithm for Buffer and Splitter Insertion in Adiabatic Quantum-Flux-Parametron Circuits. Proceedings of the 28th Asia and South Pacific Design Automation Conference (ASPDAC).

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(2022). JBNN: A Hardware Design for Binarized Neural Networks using Single-Flux-Quantum Circuits. IEEE Transactions on Computers (TC).

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(2022). A survey on superconducting computing technology: circuits, architectures and design tools. CCF Transactions on High Performance Computing (CCF-THPC).

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(2021). Equivalence Checking for Superconducting RSFQ Logic Circuits. Proceedings of the 2021 on Great Lakes Symposium on VLSI (GLSVLSI). (Best Paper Nomination)

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(2020). Design Automation Methodology from RTL to Gate-Level Netlist and Schematic for RSFQ Logic Circuits. Proceedings of the 2020 on Great Lakes Symposium on VLSI (GLSVLSI).

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