News

"Efficient Cartesian Genetic Programming-based Automatic Synthesis Framework for Reversible Quantum-Flux-Parametron Logic Circuits" is accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Jan 20, 2025 0 min read

"TeMACLE: A Technology Mapping-Aware Area-Efficient Standard Cell Library Extension Framework" is accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Jan 5, 2025 0 min read

"Buffer and Splitter Insertion for Adiabatic Quantum-Flux-Parametron Circuits" is accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Sep 6, 2024 0 min read

Seleted as DAC Young Fellow 2024

May 21, 2024 0 min read

"RCGP: An Automatic Synthesis Framework for Reversible Quantum-Flux-Parametron Logic Circuits based on Efficient Cartesian Genetic Programming" is accepted by DAC 2024

Feb 15, 2024 0 min read

"JPlace: A Clock-Aware Length-Matching Placement for Rapid Single-Flux-Quantum Circuits" is accepted by DATE 2024

Nov 8, 2023 0 min read

"Exact Logic Synthesis for Reversible Quantum-Flux-Parametron Logic" and "DLPlace: A Delay-Line Clocking-based Placement Framework for AQFP Circuits" are accepted by ICCAD 2023

Jul 21, 2023 1 min read

"BOMIG: A Majority Logic Synthesis Framework for AQFP Logic" is accepted by DATE 2023

Nov 18, 2022 0 min read

"JBNN: A Hardware Design for Binarized Neural Networks using Single-Flux-Quantum Circuits" is accepted by IEEE Transactions on Computers

Oct 3, 2022 0 min read

"A Global Optimization Algorithm for Buffer and Splitter Insertion in Adiabatic Quantum-Flux-Parametron Circuits" is accepted by ASPDAC 2023

Sep 13, 2022 0 min read