Flynn

Intelligent Design Automation Lab

CSE, CUHK

About Me

Always do what you like, do what you want, and try your best to be happy.

I am seeking a research position, please reach out for any opportunities!

Interests

Electronic design automation
Superconductive electronics
Computer architecture

Education

PhD in Computer Science, Sep 2022 - Now
The Chinese University of Hong Kong
MS in Computer Science, Sep 2018 - Jun 2021
Institute of Computing Technology, Chinese Academy of Sciences
Public Study Abroad, Dec 2017 - Jun 2018
Universidad Politécnica de Madrid
BE in Software Engineer., Sep 2014 - Jun 2018
Northwestern Polytechnical University

Experience

Internship

National Center of Technology Innovation for EDA

May 2024 – Aug 2024 Nanjing, China

Internship

Tencent

May 2021 – Jun 2021 Shenzhen, China

Internship

Meituan

Dec 2020 – Mar 2021 Beijing, China

Internship

Ant Group

May 2020 – Aug 2020 Hangzhou, China

News

4 + 1 papers are accepted by DAC 2026

Obtained the Best Poster Award of the ACM SIGDA Student Research Forum at ASP-DAC 2026

"JPnR: A Length-Matching Placement and Routing Framework for Single-Flux-Quantum Circuits" is accepted by IEEE Transactions on Computers

Seleted as DAC Young Fellow 2025

"Efficient Cartesian Genetic Programming-based Automatic Synthesis Framework for Reversible Quantum-Flux-Parametron Logic Circuits" is accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

"TeMACLE: A Technology Mapping-Aware Area-Efficient Standard Cell Library Extension Framework" is accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

"Buffer and Splitter Insertion for Adiabatic Quantum-Flux-Parametron Circuits" is accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Seleted as DAC Young Fellow 2024

"RCGP: An Automatic Synthesis Framework for Reversible Quantum-Flux-Parametron Logic Circuits based on Efficient Cartesian Genetic Programming" is accepted by DAC 2024

"JPlace: A Clock-Aware Length-Matching Placement for Rapid Single-Flux-Quantum Circuits" is accepted by DATE 2024

Publications

Zhiyuan He, Flynn, Pin-Yu Chen, Tsung-Yi Ho (2026). SAT-Helper: A Multi-Agent System for Adaptive Optimizing Large-Scale Conjunctive Normal Form. Proceedings of the 63nd Design Automation Conference (DAC). (Corresponding Author)

Yanlong Huang, Jierui Liu, Yuhan She, Flynn, Hong Yan, Tsung-Yi Ho, Ray C.C. Cheung (2026). Chariot: Compiler-Aware Heterogeneous Graph Representation Learning for Automated HLS Optimization. Proceedings of the 34th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Yanshuang Teng, Flynn, Xijie Wang, Dan Niu, Zhou Jin (2026). ELMBA: Escape from Local Minima in Buffer and Splitter Insertion for AQFP Circuits. Proceedings of the 63nd Design Automation Conference (DAC).

Flynn, Minglei Zhou, Huilong Jiang, Da Wang, Fei Wang, Huawei Cao, Junying Huang (2026). JSPlace: A Shape-Controllable and Length-Matching Placement for Rapid Single-Flux-Quantum Circuits. Proceedings of the 63nd Design Automation Conference (DAC).

Flynn, Yi Liu, Qiang Xu, Tsung-Yi Ho (2026). MappingEvolve: LLM-Driven Code Evolution for Technology Mapping. Proceedings of the 63nd Design Automation Conference (DAC).

Yaohui Han, Beichen Li, Mingyang Zhao, Flynn, Qunsong Ye, Tinghuan Chen, Bei Yu, Tsung-Yi Ho (2026). ModuPlace: LLM-Assisted Modular PCB Placement via Preference-Optimized Constraint Graph Generation. Proceedings of the 63nd Design Automation Conference (DAC). (Corresponding Author)

Flynn, Ran Zhang, Libo Shen, Wei Xuan, Ning Lin, Junying Huang, Bei Yu, Tsung-Yi Ho (2026). Efficient Multi-Array Parallel Scheduling for In-Memory Computing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).

Ran Zhang, Xinda Chen, Flynn, Chunyang He, Da Wang, Fei Wang, Tsung-Yi Ho, Junying Huang (2026). RECALLS: Reinforcement Learning Enhanced Generative Model for Logic Synthesis Optimization. IEEE International Symposium on Circuits and Systems (ISCAS).

Flynn, Ran Zhang, Ziyang Zheng, Zhengyuan Shi, Yuan Pu, Junying Huang, Qiang Xu, Tsung-Yi Ho (2025). CHOP: Clustered Hybrid Optimization for Logic Synthesis with Self-Supervised Prediction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).

Flynn, Wei Xuan, Shuo Yin, Guangyu Hu, Chen Chen, Hongce Zhang, Bei Yu, Tsung-Yi Ho (2025). eLogic: A E-Graph-based Logic Rewriting Framework for Majority-Inverter Graphs. Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE).

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