Flynn

Intelligent Design Automation Lab

CSE, CUHK

About Me

Always do what you like, do what you want, and try your best to be happy.

I am seeking a research position, please reach out for any opportunities!

Interests

Electronic design automation
Superconductive electronics
Computer architecture

Education

PhD in Computer Science, Sep 2022 - Now
The Chinese University of Hong Kong
MS in Computer Science, Sep 2018 - Jun 2021
Institute of Computing Technology, Chinese Academy of Sciences
Public Study Abroad, Dec 2017 - Jun 2018
Universidad Politécnica de Madrid
BE in Software Engineer., Sep 2014 - Jun 2018
Northwestern Polytechnical University

Experience

Internship

National Center of Technology Innovation for EDA

May 2024 – Aug 2024 Nanjing, China

Internship

Tencent

May 2021 – Jun 2021 Shenzhen, China

Internship

Meituan

Dec 2020 – Mar 2021 Beijing, China

Internship

Ant Group

May 2020 – Aug 2020 Hangzhou, China

News

"JPnR: A Length-Matching Placement and Routing Framework for Single-Flux-Quantum Circuits" is accepted by IEEE Transactions on Computers

Seleted as DAC Young Fellow 2025

"Efficient Cartesian Genetic Programming-based Automatic Synthesis Framework for Reversible Quantum-Flux-Parametron Logic Circuits" is accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

"TeMACLE: A Technology Mapping-Aware Area-Efficient Standard Cell Library Extension Framework" is accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

"Buffer and Splitter Insertion for Adiabatic Quantum-Flux-Parametron Circuits" is accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Seleted as DAC Young Fellow 2024

"RCGP: An Automatic Synthesis Framework for Reversible Quantum-Flux-Parametron Logic Circuits based on Efficient Cartesian Genetic Programming" is accepted by DAC 2024

"JPlace: A Clock-Aware Length-Matching Placement for Rapid Single-Flux-Quantum Circuits" is accepted by DATE 2024

"Exact Logic Synthesis for Reversible Quantum-Flux-Parametron Logic" and "DLPlace: A Delay-Line Clocking-based Placement Framework for AQFP Circuits" are accepted by ICCAD 2023

"BOMIG: A Majority Logic Synthesis Framework for AQFP Logic" is accepted by DATE 2023

Publications

Flynn, Ran Zhang, Ziyang Zheng, Zhengyuan Shi, Yuan Pu, Junying Huang, Qiang Xu, Tsung-Yi Ho (2025). CHOP: Clustered Hybrid Optimization for Logic Synthesis with Self-Supervised Prediction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).

Flynn, Wei Xuan, Shuo Yin, Guangyu Hu, Chen Chen, Hongce Zhang, Bei Yu, Tsung-Yi Ho (2025). eLogic: A E-Graph-based Logic Rewriting Framework for Majority-Inverter Graphs. Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE).

Yaohui Han, Beichen Li, Flynn, Qunsong Ye, Zhiyuan Lu, Junchen Liu, Bei Yu, Tsung-Yi Ho, Tinghuan Chen (2025). PCB-Migrator: Automated PCB PnR Migration. Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE).

Flynn, Minglei Zhou, Siyan Chen, Xinda Chen, Junying Huang, Xiaochun Ye, Zhimin Zhang, Tsung-Yi Ho (2025). JPnR: A Length-Matching Placement and Routing Framework for Single-Flux-Quantum Circuits. IEEE Transactions on Computers (TC).

Flynn, Libo Shen, Ziyi Wang, Zhengxing Lei, Zixiao Wang, Junying Huang, Bei Yu, Tsung-Yi Ho (2025). DCLOG: Don't Cares-based Logic Optimization using Pre-training Graph Neural Networks. Proceedings of the 31st Asia and South Pacific Design Automation Conference (ASPDAC).

Shuo Ren, Zhen Zhuang, Flynn, Leilei Jin, Libo Shen, Bei Yu, Tsung-Yi Ho (2025). Partitioning-free 3D-IC Floorplanning. Proceedings of the 31st Asia and South Pacific Design Automation Conference (ASPDAC).

Leilei Jin, Flynn, Zhen Zhuang, Liang Xiao, Fangzhou Liu, Bei Yu, Tsung-Yi Ho (2025). ChronoTE: Crosstalk-Aware Timing Estimation for Routing Optimization via Edge-Enhanced GNNs. Proceedings of the 44th IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Flynn, Minglei Zhou, Huilong Jiang, Junying Huang, Xiaochun Ye, Tsung-Yi Ho (2025). J2Place: A Multiphase Clocking-Oriented Length-Matching Placement for Rapid Single-Flux-Quantum Circuits. Proceedings of the 44th IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Minglei Zhou, Flynn, Ran Zhang, Xiaochun Ye, Tsung-Yi Ho, Junying Huang (2025). An Optimal DFF-Oriented Technology Legalization Algorithm for Rapid Single-Flux-Quantum Circuits. Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI).

Yang Su, Sheng Li, Huilong Jiang, Haofei Yin, Flynn, Junying Huang, Xiaochun Ye, Zhimin Zhang, Jie Ren, Xiaoping Gao, Tsung-Yi Ho, Dongrui Fan (2025). JBSA: A Bit-Serial Accelerator for Deep Neural Networks Using Superconducting SFQ Logic. ACM International Conference on Supercomputing (ICS).

See all publications