Experience

 
 
 
 
 

Internship

Tencent

May 2021 – Jun 2021 Shenzhen, China
 
 
 
 
 

Internship

Meituan

Dec 2020 – Mar 2021 Beijing, China
 
 
 
 
 

Internship

Ant Group

May 2020 – Aug 2020 Hangzhou, China

News

Publications

(2024). RABER: Reliability-Aware Bayesian-Optimization-based Control Layer Escape Routing for Flow-based Microfluidics. Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

DOI

(2024). FlatDD: A High-Performance Quantum Circuit Simulator using Decision Diagram and Flat Array. Proceedings of the 53rd International Conference on Parallel Processing (ICPP).

(2024). RCGP: An Automatic Synthesis Framework for Reversible Quantum-Flux-Parametron Logic Circuits based on Efficient Cartesian Genetic Programming. Proceedings of the 61st Design Automation Conference (DAC).

PDF DOI

(2024). JPlace: A Clock-Aware Length-Matching Placement for Rapid Single-Flux-Quantum Circuits. Proceedings of the 27th Design, Automation & Test in Europe Conference & Exhibition (DATE). (co-first author)

PDF URL

(2023). DLPlace: A Delay-Line Clocking-Based Placement Framework for AQFP Circuits. Proceedings of the 42nd IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

PDF DOI

(2023). Exact Logic Synthesis for Reversible Quantum-Flux-Parametron Logic. Proceedings of the 42nd IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

PDF DOI

(2023). JRouter: A Multi-Terminal Hierarchical Length-Matching Router under Planar Manhattan Routing Model for RSFQ Circuits. Proceedings of the 2023 on Great Lakes Symposium on VLSI (GLSVLSI).

PDF DOI URL

(2023). BOMIG: A Majority Logic Synthesis Framework for AQFP Logic. Proceedings of the 26th Design, Automation & Test in Europe Conference & Exhibition (DATE).

PDF DOI URL

(2023). A Global Optimization Algorithm for Buffer and Splitter Insertion in Adiabatic Quantum-Flux-Parametron Circuits. Proceedings of the 28th Asia and South Pacific Design Automation Conference (ASPDAC).

PDF DOI URL

(2022). JBNN: A Hardware Design for Binarized Neural Networks using Single-Flux-Quantum Circuits. IEEE Transactions on Computers (TC).

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